1. Field of the Invention
The present invention relates to a display signal interface system between a display controller, such as a computer, and a display apparatus.
2. Description of the Related Art
Recently, with the development of personal computers, there is a tendency that various resolutions are adopted in display apparatuses. An example of a typical display mode is VGA mode (640 dots.times.480 lines). In addition, there is a tendency that SVGA mode (800 dots.times.600 lines) and XGA mode with a higher resolution (1024 dots.times.768 lines) are adopted.
With an increase in resolution, however, the amount of information transferred from a display controller to a display panel increases. Thus, the frequency of a display clock signal increases and the number of interface signal lines between the display controller and the display apparatus increases as well. For example, in the case of the VGA mode, the clock frequency is about 25 MHz and data is input directly to the display panel. Thus, the interface has no special structure. Specifically, the interface is a digital interface, and data is transferred directly to a flat panel display at a clock frequency of 25 MHz.
On the other hand, in order to activate a TFT panel (displayable in 260,000 colors) with a display resolution of 1024.times.768 dots, the clock output from the display controller needs to be 65 MHz and the number of data lines output from the display controller needs to be 18 (6 R-lines, 6 G-lines, and 6 B-lines). In the case of a TFT panel with a display resolution of 800.times.600, the clock frequency is 40 MHz. On the other hand, the display controller and the display apparatus are connected to each other via a connector and a harness. It is difficult, in view of electric waves, to transfer display data at such a high clock frequency from the standpoints of, e.g. set-up time and hold time (timing and skewing are difficult). In addition, since display data is transferred at a relatively high voltage (at TTL level of about 5 V), the influence by electric wave radiation upon the ambience is great.
Under the circumstances, there is an idea that the number of data lines is doubled, without inputting data directly to the flat panel, thereby the frequency of the shift clock is reduced to 1/2. In this method, the number of data lines is multiplied and the interface between the display controller and flat panel is complicated.
Jap. Pat. Appln. KOKAI Publication No. 1-118196 discloses a transfer system wherein digital display data (16-bit gradient data) output from a display controller is converted to a low-voltage analog serial signal by a D/A converter and transferred to a display apparatus, and the analog serial signal is converted to a digital display signal by an A/D converter on the display apparatus side, and further the digital display signals for four pixels are put together by a serial/parallel conversion circuit and transferred to a flat panel in parallel. Besides, Jap. Pat. Appln. KOKAI Publication No. 1-118195 discloses a system wherein digital display data output from a display controller is converted in parallel by a serial/parallel conversion circuit and transferred in parallel to the display apparatus side as low-voltage analog signal by a D/A converter, and on the display apparatus side the received parallel display data is converted to a digital display signal by an A/D converter and supplied to a flat panel.
Furthermore, Jap. Pat. Appln. KOKAI Publication No. 2-77083 discloses a display clock signal transfer system wherein, in a clock transfer mechanism between a display controller and a flat display panel, a display clock signal output from the display controller is converted to a low-potential clock signal and transferred to a flat panel display, and the low-potential clock signal is boosted on the flat panel display side and supplied to the flat panel display. Although this document shows means for preventing the influence of electric wave radiation upon the ambience, it is silent on the means for solving problems relating to an increase in number of signal lines of interface signals between the display controller and display apparatus in a high-resolution display mode, an increase in speed of shift clocks, etc.
As has been described above, in the prior art, display signals are transferred between the display controller and display apparatus at a relatively high voltage (CMOS/TTL level) and at a higher clock frequency in accordance with higher resolution display. Thus, a radio wave interference occurs and it is difficult to obtain timing and skew adjustments. On the other hand, if the transfer shift clock is divided, the number of data lines increases and the interface between the display controller and flat panel is complicated. Besides, in order to reduce the influence on the ambience as much as possible, a more effective countermeasure to electromagnetic interference (EMI) has been desired.